1. Field of the Invention
The present invention relates to a scan path and, more particularly, to a scan path provided on the periphery of an asynchronous RAM core and a logic circuit.
2. Description of the Background Art
FIG. 16 is a block diagram of a structure for performing a test technique using a scan test method wherein scan paths 1 to 3 are provided for a logic region 80 including three logic portions 81 to 83 and an asynchronous RAM core 91 surrounded by the logic region 80. In the scan test method, flip-flops (FFs) within a chip are replaced with scan flip-flops (SFFs) to form a scan path.
With reference to FIG. 16, for example, a serial scan-in signal SI1 which is test data is sequentially applied to the scan paths 1 to 3, and a test result is outputted in the form of a serial scan-out signal SO after the execution of the test. The scan paths 1 and 2 and the RAM core 91 constitute a RAM block 92.
FIG. 17 is a detailed circuit diagram of the RAM block 92. The scan path 1 comprises scan flip-flops 10 to 12, and the scan path 2 comprises scan flip-flops 20 to 22 and selectors 203, 213, and 223. Each of the scan flip-flops 10 to 12, and 20 to 22 includes a selector having a "0" input and a "1" input which are connected to an output thereof when a control signal is "0" and "1", respectively, and a flip-flop connected to the output of the selector.
FIG. 18 is a circuit diagram of the scan flip-flop 10. The scan flip-flop 10 comprises a selector 101 and a flip-flop 102. Other scan flip-flops may be similar in construction to the scan flip-flop 10. All of the scan flip-flops 10 to 12, and 20 to 22 shown in FIG. 17 receive a shift mode signal SM serving as a control signal therefor.
During a normal operation, the shift mode signal SM is set to "0", and the scan flip-flops 10 to 12 and the scan flip-flops 20 to 22 function as normal flip-flops provided at the inputs and outputs of the RAM core 91, respectively.
However, the scan flip-flops 20 to 22 of the scan path 2 provided at the output of the RAM core 91 sometimes perform their substantial function and sometimes do not, depending upon the function of the selectors 203, 213, and 223 for selectively providing the outputs from the scan flip-flops 20 to 22 and the outputs from the RAM core 91. More specifically, the RAM block 92 performs a synchronous/asynchronous read operation in response to the value "1"/"0" of a test mode signal TEST provided as a control signal for the selectors 203, 213, and 223. The term "synchronous" used herein means "in synchronization with" a clock essentially required for operation of flip-flops and the like and not shown.
During a test operation (logic test) for the logic region 80, the shift mode signal SM and the test mode signal TEST are set to "1" to cause the scan flip-flops 10 to 12, and 20 to 22 to sequentially shift the scan-in signal SI1 (in a scan mode) until test data are stored in the scan flip-flops 20 to 22.
The test data are applied to the logic portion 82. Since the scan path 1 receives the outputs (test result) from the logic portion 81, the scan flip-flops 10 to 12 store the test result therein.
In this manner, all of the scan flip-flops 10 to 12, and 20 to 22 are used for the logic test. However, when the synchronous write operation and asynchronous read operation are required as the functions of the RAM block 92, the scan paths 20 to 22 do not perform their substantial function during the normal operation. Additionally, the use of the scan path 3 is not required for testing only the RAM core 91. These facts cause an area overhead in the scan flip-flops 20 to 22 or the scan path 3, resulting in a low area utilization efficiency.